Rosario Attanasio, STMicroelectronics – Italy – rosario.attanasio@st.com
Francesco Gennaro, STMicroelectronics – Italy – francesco.gennaro@st.com
Abstract
AC/DC converters for applications such as laptop adapters require to achieve high efficiency
over the entire load range of operation and across the universal mains input voltage range.
Given the demand for more efficient, smaller adapters their design is becoming more challenging
and new conversion approaches, other than the standard ones are being investigated
as possible alternatives. In particular while, the standard approach is based on the use of
a boost type PFC with a 400V DC output and a regulation stage, generally implemented with
a half bridge topology, an alternative two stage architecture can also be considered for high
density, high efficiency adapters. In this last case, a buck type PFC front-end stage is used,
followed by the output isolation and regulation stage implemented using a Half-Bridge topology.
This paper deals with the performance comparison of the two approaches with particular
ttention on practical issues like size and cost of passive components, efficiency and
power quality. Simulation results are provided to support some of the main conclusions to
this analysis.
1. Introduction
In fig. 1 is shown a simplified schematic of a standard AC/DC converter. A two stage architecture
is generally implemented in this kind of applications. The first stage is a Boost PFC
operating with universal input voltage and producing a regulated high output voltage. The
output isolation and regulation stage is implemented using a Half-Bridge topology operated
with a standard PWM modulation. Both the PFC stage and DC/DC stage operate in Continuous
Current Mode (CCM) and neither optimized modulation techniques or soft switching are
used in order to increase the efficiency across the full load range. The Boost PFC is typically
controlled using an outer voltage loop to regulate the bus voltage to the desired value and
an inner control loop to shape the current according to a sinusoidal waveform. The outer
loop adjusts the current reference in order to maintain a regulated bus voltage independently
from the load or input voltage variations. The DC/DC stage performs a voltage step down
using a HF transformer with a primary to secondary turns ratio chosen to maintain a good efficiency
in the whole operating range. The transformer is supplied with a square wave voltage
generated by the primary side active devices. On the secondary side this voltage waveform
is rectified and then smoothed by the output LC filter. The overall efficiency of such a
topology should be comprised between 80% and 90% depending on the optimization level.
Fig. 1. Simplified schematic of a standard AC/DC converter.
In Table I are listed the main system specifications.
Table I: 300W AC-DC adapter with PFC and DCDC converter specifications.
The input stage of an AC/DC circuit can also be implemented using a Buck converter. In this
case, the output voltage of the input circuit has to be lower than the minimum peak input
voltage. For this application an output voltage value of 45V DC has been chosen. Thanks to
this choice, the DC-DC regulation stage performs a low voltage conversion ratio and can be
designed with semiconductors rated for a lower breakdown voltage compared to the boost
PFC case. As for the first design based on the use of a boost PFC, the switching frequency
of both the conversion stages is fixed and equal to 100 kHz. The simplified schematic of
such a topology is shown in fig.2, where the control scheme consisting of a voltage loop and
an inner current loop is also shown.
Fig. 2. Simplified schematic of the holistic AC/DC converter.
Table II gives a summary of the specifications of the two converters used for the implementation
of the holistic AC/DC converter. The main requirements, such as current ripple, voltage
ripple and hold up time are basically the same as in the previous design. This second
design, is carried out considering a buck PFC with universal input voltage range and 45V DC
output. The DCDC stage is still an isolated Half Bridge converter performing voltage step
down from 45V to 12V. ‘
Table II: 300W Holistic AC/DC adapter with PFC and DCDC converter specifications.
The maximum current Ipk which flows through the inductor is first calculated. The maximum
peak line current Ipk, corresponds to the minimum operating voltage at maximum output
power. The same assumptions on efficiency of the standard approach design are used also
for the holistic design.
2. Comparison between the Standard and Holistic AC/DC Converter
This section presents the performance comparison of the two implementations which has
been carried out through simulations and theoretical considerations. The comparison is
based on the following assumptions:
1) The input rectifier losses, inductor losses, EMI filter losses are not taken into account
for both the topologies.
2) The power components of each topology have been chosen to realize the best compromise
in terms of efficiency and cost.
3) Both the topologies have the same switching frequency and operate in Continuous
Conduction Mode (CCM)
4) The switching frequency is constant independently of the operating point.
The main components values and part numbers used for the simulation of the two converters
are shown in table III.
Table III: Summary of main design parameters for the two AC/DC solutions.
The first thing to notice is the difference in the resulting hold up capacitor values. Interesting
to highlight how high the capacitance value is for the Holistic AC/DC converter as a consequence
of the low output voltage of the buck PFC, being capacitance inversely proportional
to the square of voltage. This is definitely an aspect to carefully take into account for the
practical implementation of the holistic AC/DC converter as well as when considering system
integration. On the other side, the low output voltage of the buck PFC converter allows the
use of low voltage power devices in the DC/DC stage, with clear advantages in terms of
losses reduction and therefore efficiency. The advantage comes from the lower drain to
source resistance of these devices compared to the high voltage ones used for the DC/DC
of a standard AC/DC solution. Also, table VI shows the selected part numbers for the buck
and boost PFC implementations. It can be noticed that the buck PFC power device has a
lower breakdown voltage compared to the main power device of the boost PFC. In fact, while
the Buck PFC has to safely withstand the maximum input voltage, the boost PFC has to
withstand the 400V DC output. This results in the choice of a 500V Mosfet for the buck PFC
of the holistic converter and a 650V device for the boost PFC of the standard solution.
The advantage coming from the use of lower rated devices, in terms of breakdown voltage,
is totally counteracted by the higher operating output current of the buck PFC. In fact, the
conduction losses of the buck PFC diode are almost twice those of the boost PFC converter.
As a consequence, the input stage of the holistic converter has a lower efficiency compared
to the input stage of a standard solution. From an overall system efficiency point of view, this
disadvantage is partially counteracted by a better performing DCDC converter. Such considerations
can be extracted from the two diagrams in fig. 3 where the breakdown of the losses
of the two implementations is presented both for a 90V and a 265V AC input voltage. While
in both the applications the PFC Mosfet losses are comparable, the diode PFC losses are a
lot higher for the buck implementation and have a big impact on the resulting system efficiency.
Also the total losses in the DC/DC stage are quite similar for the two implementations.
Fig. 4 and fig. 5 show the efficiency characteristics of the two topologies as a function
of the output power when the input voltage is fixed either at 90V AC or 265V AC and as a
function of the input voltage at a given load condition, respectively. The holistic implementation
seems to be more efficient in the low power/low voltage range. In fact, at 90 V AC input
the holistic converter is more efficient than the standard one when operating below 200W.
For an input voltage of 265 V AC the standard implementation is more efficient than the holistic
over the entire load range due to the reduced conduction and switching losses of the
power devices.
Fig. 3. Breakdown of losses at 300W and 90V AC and 300V AC input.
Fig. 4. Efficiency comparison across the operating power range at 90Vac input and 265Vac.
Fig. 5. Efficiency comparison across the input voltage at fixed load condition: 10%, 50% and 100%
rated output power.
There is a strong correlation between input voltage, output power and efficiency of the two
topologies. The holistic implementation seems to be a better option only if the input voltage
is maintained below 150V AC and the output power doesn’t exceed 100W. In this case, the
efficiency gain compared to the standard solution is comprised between 10% and 1% depending
on the electrical load.
For a fair comparison some other aspects, such as power quality and EMC performance
have to be taken into account beyond efficiency.
Regarding power quality, the input current THD and power factor are the main aspect to take
into account. Fig.6 shows the simulation results used to evaluate the comparison in terms of
input current shaping capabilities of the two implementations. The voltage step down characteristic
of the buck converter makes the input current shaping impossible when the input
voltage is lower than the output voltage. As shown in fig.6, when the input voltage falls below
the output voltage no power can be drawn from the AC line with an evident impact on the
input current shape which shows a kind of dead time in proximity of the input voltage zero
crossings. This problem also limits the power factor of this topology. As a consequence, the
holistic converter has a higher input current THD and lower power factor compared to a conventional
AC/DC converter adopting a boost PFC.
Fig. 6. Simulation results showing the power quality of the input current for the standard (a) and holistic
(b) AC/DC converter.
Finally, from an EMC point of view, the low voltage swing of buck PFC switch should result in
better EMI performance than the boost PFC. As a consequence, the loss of the common
mode choke of the boost EMI filter is expected to be greater than that of the buck because
the attenuation of higher common-mode currents, requires bigger values of the filter components.
In conclusions, the size, cost and losses of the boost PFC EMI filter are supposed to
be greater than those of the buck PFC.
3. Conclusion
This paper deals with the performance comparison of a standard and a holistic AC/DC converter
rated at 300 W and operating with universal input voltage. Starting from the definition
of suitable specifications, the first section of the document shows a step by step design procedure
cedure to define the main ratings and values of both the active and passive components
used for the two implementations. The resulting design values have been used to perform
simulations and theoretical calculations of the main losses characterizing the two topologies.
The results of both simulations and calculations were used to provide realistic projections of
the efficiency and general performance of the two AC/DC converters as a function of input
voltage and electrical load.
The main results of this analysis show that even if the holistic converter is a possible option
to the standard approach, some constraints have to be taken into account during the design
phase, before proceeding with an actual implementation. First of all, these considerations
are related to the efficiency of the holistic converter which seems to be better than the
standard one only when operating with low input voltage values, below 120V AC, and for
output power levels lower than 100W. Outside this operating window, the holistic converter is
generally 1% to 3% less efficient than the standard one.
The second thing to consider is related to power quality. The holistic converter uses a buck
PFC input stage which suffers of inherent input current distortion in proximity of the input
voltage zero crossings. This causes the current THD to be higher than the one recorded for
the boost PFC and the power factor to be lower.
On the other hand the EMC performance of the holistic converter is supposed to be better
than that of the boost converter for the fact that the main power device is subjected to lower
voltage stress.
From a practical implementation point of view, given the demand for smaller conversion systems,
designed for high power density, the high value of the hold up capacitor seems to be a
further disadvantage compared to the standard approach. Nevertheless, from a cost point of
view, the holistic solution seems to be more effective thanks to the use of lower voltage rated
power devices in both the conversion stages and potentially smaller EMI filters.
4. Literature
[1] Chen Bing, Xie Yun-Xiang, Huang Feng and Chen Jiang-Hui: A Novel Single-phase Buck PFC Converter
Based on One-cycle Control, Power Electronics and Motion Control Conference, 2006. IPEMC
2006. CES/IEEE 5th International, 14-16 Aug. 2006, pp.: 1 - 5
[2] L. Huber, Liu Gang, M. M. Jovanovic: Design-Oriented Analysis and Performance
Evaluation of Buck PFC Front End, IEEE Transaction on Power Electronics, Vol.25, n.1, January 2010,
pp. 85-94
[3] B. Keogh, G. Young, H. Wegner, C. Gillmor: Design Considerations for High Efficiency Buck PFC
with Half-Bridge Regulation Stage, Twenty-Fifth Annual IEEE Applied Power Electronics Conference
and Exposition (APEC), 2010.
